1. Field of the Invention
The present invention relates to a configuration of signal lines in a semiconductor integrated circuit, in particular, a configuration of signal lines which can realize a high access speed and a reduction of chip size simultaneously.
2. Discussion of Background
A semiconductor integrated circuit has been improved variously in order to obtain a high access speed. As one of these improvements, a method that, in a semiconductor integrated circuit having memories, a line called data line, through which data to be read out from a memory cell or data to be written in a memory cell is transmitted, is composed of a pair of signal lines; and data to be read out from the memory cell or data to be written in the memory cell are transmitted through the paired data line has been widely used. When the data read out from the memory cell or the data to be written in the memory cell is transmitted to the paired data lines which have been pre-charged in advance, the data exist in the paired data lines have values which are complementary to each other. Provided that the data read out from the memory cell or the data to be written in the memory cell are called valid data, in a case that the data lines are composed to have paired structure, a time when data transmitted through the paired data lines have values complementary to each other is a time when the valid data are transmitted.
As a configuration of paired data lines, for example, there is proposed a semiconductor integrated circuit disclosed in Japanese Unexamined Patent Publication Hei 2-101773 (JP-A-2-101773), wherein the semiconductor integrated circuit is composed such that data lines are constituted to be paired and countermeasures against the increment of the number of data lines caused by increasing bits and expanding capacities in recent dynamic random access memories (DRAM) are disclosed.
Meanwhile, FIG. 32 is a block diagram for showing prior art in which only single data lines are used to connect a preamplifier with a main amplifier of an ordinary DRAM.
In FIG. 32, a numerical reference 001 designates an array block of the DRAM. An i/o line area 200 is constituted by a plurality of paired i/o lines; and a preamplifier area 300 is constituted by preamplifiers pa0 through pan, which are provided in correspondence with the paired i/o lines respectively. Data in a memory cell in the memory cell array block 100 read out through the paired bit lines are amplified by the preamplifiers pa0 through pan after passing through paired i/o lines respectively. Data line area of a first system 400 is composed of single data lines rd0 through rdn, each one of which is connected to a corresponding preamplifier among the preamplifiers pa0 through pan, and transmits the data of memory cell amplified by the preamplifiers pa0 through pan. These data transmitted through the data lines rd0 through rdn of the first system are held temporarily in an intermediate latch circuit area 500 composed of intermediate latch circuits la0 through lan, which are respectively connected to the data lines rd0 through rdn of the first system; transmitted through single data lines od0 through odn in a data line area of a second system 600, each one of the single data lines od0 through odn connected to a corresponding intermediate latch circuit among the intermediate latch circuits la0 through lan; and reached to main amplifiers ma0 through man respectively in a main amplifier area 700. Further, these main amplifiers ma0 through man output from input/output terminals dq0 through dqn in a group of input/output terminals 010 to the outside.
FIG. 33 is a timing chart for showing an operation of conventional DRAM shown in FIG. 32.
In FIG. 33, references i/o, /i/o designate data in memory cell transmitted through paired bit lines and a sense amplifier to the paired i/o lines. In this, a case that identical data are read out so as to be transmitted the paired i/o lines represented by 0 through n. A reference pae designates a preamplifier activation signal; a reference rdi designates data to be transmitted through one of the single data lines of the first system rd0 to rdn; a reference rdL designates a signal for controlling data holding of the intermediate latch circuits la0 through lan; a reference odi designates data to be transmitted through one of the data lines of the second system od0 to odn which are outputs from the intermediate latch circuits la0 to lan; a reference oem designates an output control signal of the main amplifier, which is generated by delaying the signal for controlling data holding rdL; and a reference dqi designates data to be output from one of the input/output terminals dq0 through dqn. In the Figure, a reference (HO) designates a case that the data output from the one of the input/output terminals dq0 through dqn are data of a high level (H level), and a reference (L0) designates a case that the data are of a low level (L level).
Data in a memory cell in an address designated at a time T00 appear in paired i/o lines through paired bit lines and the sense amplifier.
At a time T01, the preamplifier activation signal pae becomes the H level and the preamplifier is activated. The data of the memory cell appeared in the paired i/o lines are subjected to a differential amplification by the activated preamplifier and the L level is output to one of the data lines of the first system rd0 through rdn.
The signal for controlling data holding rdL of the intermediate latch circuit, which is in the H level in advance at a time T02, becomes the H level by a delay of the preamplifier activation signal pae. In accordance with this change, the data transmitted from the one of the data lines of the first system rd0 through rdn is held in the intermediate latch circuit and output to one of the data lines of the second system od0 through odn. The period between the time T01 and the time T02 is designed based on a result obtained by calculating accurately and predicting by a simulation or the like in advance such that the amplified data outputs from the preamplifiers pa0 through pan are transmitted through the data lines of the first system rd0 through rdn, arrive at the intermediate latch circuits la0 through lan, and are held securely therein.
At a time T03, the output control signal oem of the main amplifier is activated, in other words, becomes the H level. In response thereto, transmitted data are output from one of the input/output terminals dq0 through dqn by the maim amplifier. Timing for activating the output control signal oem is also designed based on a result obtained by calculating minutely a time when data to be transmitted through one of the data lines of the second system od0 through odn arrive at a corresponding main amplifier by a simulation or the like, in a similar manner to that of the timing of the above-mentioned signal for controlling data holding rdL.
However, the conventional semiconductor integrated circuit has a problem that a size of chip became unfavorably large because, for example, when all of data lines were constituted by pairs of lines, the data lines occupied a very large area for wiring in a chip area of the semiconductor integrated circuit in accordance with an increasing number of pins, a configuration of bank and an increasing bit capacity, which have been especially prevailing in recent years, and therefore the size of chip in the semiconductor integrated circuit was restricted by the area for wiring.
Further, there were problems that wiring of paired data lines for obtaining a high speed became extraordinarily long because a layout of semiconductor integrated circuit is restricted by an increment of the number of wirings and the data lines had to be provided in a wiring layer having a high resistance value and a high capacitance value. Further, there was a problem that a yield was affected because connections between different wiring layers had to be realized by contacting these as a result of a complicated layout and thereby a defective opening of contact, a disconnection of wire, a short circuit and so on are apt to occur at a time of manufacturing the semiconductor integrated circuit.
On the other hand, in a case of the structure shown in FIG. 32, the area for wiring becomes about a half of that in comparison with that in the structure made of paired data lines, whereby it was very effective for reducing the size of chip. However, it was necessary to conduct a simulation by considering or assuming various elements such as every data line, a wiring length of signal line, a configuration of lines, a material of line and a margin of operating temperature in order for setting functional timings of the signals rdL and oem for controlling the data holding in the intermediate latch circuit, an output from the main amplifier and so on. Further, in such case, there was a problem that a high speed operation was not effectively conducted because the timings of control signals were set based on a case that transmission of data was slowest, namely, the worst condition.
Further, there was a problem that a yield was greatly affected because a delicate adjusting of the timing introduces malfunctions depending on a scattering in a manufacturing process.
Practically, a semiconductor integrated circuit using paired data lines for most of data lines in order to attain a high speed operation is increasingly used despite that a large capacity of the semiconductor integrated circuit is pursued in these several years.